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UDC 519.872

TO THE QUESTION OF ASSESSING SERVICE TIME OF TRANSACTIONS OF DATA EXCHANGE IN MULTIPROCESSOR SYSTEMS BASED ON SHARED BUS WITH SHARED MEMORY

A. I. Martyshkin Ph.D. (technical sciences), associate Professor at the Department of computers and systems, PSTU, Penza; This email address is being protected from spambots. You need JavaScript enabled to view it.
The article deals with the evaluation of the time of service orders (transactions) in the exchange of data in multi-processor systems with shared (common) memory based on a common bus. The aim is to study models subsystem "processor-memory" and to assess applications service time during communication in multiprocessor systems with shared memory. The subject of study of this work is the analysis of time delays that are associated with conflicts when accessing multiple processors sharing a common bus and the memory of carrying out interprocessor exchange. The objects of study of this work are multiprocessor system "processor-memory" subsystem, existing variety of building this architecture subsystem. The main objective, which is set by the author, is the development of mathematical models of multiprocessor systems "processor-memory" subsystem and evaluation of incoming transaction processing time for data exchange in the shared memory systems. On the mathematical models proposed the time of transaction services is studied, the expression for probability-time characteristics of circulation time to "processor-memory" subsystem is derived. Models are viewed using the apparatus of queuing theory and probability theory. In conclusion, relevant findings are made. The above article models allow us to assess the characteristics of multi-processor systems without building a real layout. Due to this economic effect is achieved, since the assessment of the projected system performance and the choice of best options may be carried out without the construction of a real system.

Key words: simulation, analytical model, simulation model, system of mass service, transaction, a read operation, a record operation, multiprocessor system, "processor-memory" subsystem, memory architecture, memory bandwidth, memory controller, memory latency, buffer element.