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UDC 621.382

DETAILED STUDY OF SLOW TRAPS IN GATE DIELECTRIC OF MOSFET USING CONSECUTIVE MEASUREMENTS OF TRANSIENT RESPONSE

V. E. Drach, PhD (technical sciences), assistant professor, Bauman MSTU (Kaluga branch), Kaluga; This email address is being protected from spambots. You need JavaScript enabled to view it.

For a MOSFET, the measurement of ID-VG curves can be performed repeatedly, but all the curves will be identical. But if a MOSFET was stressed (for example, by Fowler-Nordheim injection), and then had a discharge phase, further measurements will yield different sets of curves - in other words, there is a "shift" of the ID-VG characteristics. To study the ID-VG shift, a special measurement procedure was developed, which constituted two phases, namely, the discharge process phase and ID-VG measurement phase. The ID-VG shift is observed in a set of two consecutively measured forward-mode ID-VG curves. Two characteristics are used to characterize the above phenomenon, namely, the difference ΔID,IVH between the two consecutively measured IDVG curves and the threshold voltage difference ΔVth,IVH between the two consecutively measured ID-VG curves. In this paper, the ID-VG hysteresis and the slow border traps are systematically studied, including the origin of the phenomenon, the physical nature and significance of the phenomenon, the charging characteristics and process of the slow border traps, influencing factors, and the parameters used to characterize the phenomenon. The possibility to use the phenomenon as a convenient tool to study the slow border traps and a degradation monitor is discussed.

Key words: gate dielectric, MOS structure, MOSFET, ID-VG, traps, charging, discharging.

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