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UDC 681.32

PARAPHASE MAJORITY ELEMENT WITH THE SPASER INPUT

S. F. Tyurin, Honored Inventor of the Russian Federation, PhD (technical sciences), Professor at the Department of Automation and Telemechanics, Perm National Research Polytechnic University; This email address is being protected from spambots. You need JavaScript enabled to view it.
A. N. Kamenskih, PhD student, assistant lecturer of the Faculty of Electrical Engineering, the department of Automation
and Remote Control, Perm National Research Polytechnic University; This email address is being protected from spambots. You need JavaScript enabled to view it.

Fault-tolerant systems use redundancy with the choice, for example, «two of three», carried out by the majority element. To increase the probability of failure-free operation of digital equipment not one but three majority elements are often used. The implementation of the majority element in CMOS transistors requires 10 of these transistors. 5 p-conduction transistors realize a connection to power bus, 5 n-conduction transistors - connection to «zero volts» bus, with wiring diagrams having similar effect due to self-dual majority function. This produces a majority inversion function. To receive the majority itself inverse function arguments are required. Self-timed circuits (STC), promising in terms of energy efficiency and fault tolerance, use discipline paraphrase supply variables, and therefore simply realized paraphrase majority element.
When all inputs are of the same value, for example, zero, at main and inverse outputs of majority element identical values (true) are set. However, in some cases, it is complicated by the fact that some of memory cells connected to the elements of the majority, have no such function. The aim of the work is to realize and study of majority element for STC with spacer phase. The simulation of CMOS majority element in NI Multisim 10 firm National Instruments Electronics Workbench Group circuit simulation system is carried out. We introduce enable input, providing spacer phase. Simulation confirms efficiency of the scheme. In order to increase the probability of failure-free operation triple redundancy enable input is performed. The
patent of the Russian Federation is obtained for technical solution of the problem.

Key words: majority element, Cmos transistor, self-timed circuits.

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