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UDC 681.32

SELF-TIMED LOOK UP TABLE

S. F. Tyurin, Honored Inventor of the Russian Federation, Doctor of Technical Sciences, Professor at the Department of Automation and Telemechanics, Perm National Research Polytechnic University; This email address is being protected from spambots. You need JavaScript enabled to view it.
A. Yu. Skornyakova, post-graduate student of the Perm National Research Polytechnic University, Department of Automation and Telemechanics; This email address is being protected from spambots. You need JavaScript enabled to view it..

The problem of self-timed look up table use is studied. The version of look up table is proposed. The look up table is adjusted by constants at the constructing stage of uncommitted logic arrays without using RAM and switch fabrics in order to unify logic and reduce the design complexity. The purpose of this article is to design and research the look up table for development of self-timed circuits. Design of look up table for selftimed circuits (LUT-ST) is completed in NI Multisim 10 electronic schematic capture and simulation program by National Instruments Electronics Workbench Group. The program provides confirmation of technical solution efficiency. The article describes the principle of obtaining self-timed look up table from 1-LUTс element with inverters at input variables. A simulation of these elements is performed at the operational and spacer stages.

Key words: CMOS transistor, self-timed circuits, look up table, operational stage, spacer stage, paraphase channel, inverter, logical element.

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