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UDC 004.72

ANALYSIS OF VLSI DESIGN COMPLEXITY BY MEANS OF HYBRID HIERARCHICAL CLIENT-SERVER SUBSYSTEM

V. M. Glushan, PhD (technical sciences), full professor, SFEDU, Taganrog; This email address is being protected from spambots. You need JavaScript enabled to view it.
I. A. Dubrovsky, student, SFEDU; This email address is being protected from spambots. You need JavaScript enabled to view it.
O. I. Krasyuk, student, SFEDU; This email address is being protected from spambots. You need JavaScript enabled to view it.
M. V. Rybalchenko, PhD (technical sciences), associate professor, SFEDU; Taganrog, This email address is being protected from spambots. You need JavaScript enabled to view it.

This work contains the analysis of the complexity of VLSI design by means of hybrid hierarchical clientserver architecture. The aim of this work is to reveal speed capabilities of VLSI design subsystems built upon homogeneous and hybrid hierarchical client-server architectures. The underlying expression of the imitation research process is given here. The following four main design components are counted in the expression: distribution (decomposition) of a circuit over client computers being on different levels of hierarchical architecture; placing elements in each sub circuit performed by last-level computers; connection routing in each sub circuit; external connection routing between circuits transferred from the last level to the zero level. It is presumed that all the algorithms have polynomial complexity. Hypergraphs are used as the model of circuits. In program emulator, random circuit parameter setting is provided: number of elements, number of element’s contacts, branching effort. The emulator outputs the main numerical characteristics on the basis of which, it plots graphical dependencies of steps number and external connections number for each hierarchical architecture which make the main contribution to the complexity of design process.

Key words: hierarchical client-server architecture, VLSI, emulation, hypergraph, circuit decomposition, placing, routing.

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