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UDC 621.3.049.771.14:004.021

DEVELOPMENT OF LOGICAL RESYNTHESIS METHODS FOR FPGAS BASED ON LOGICAL CELLS WITH BUILT-IN TRIGGER

I. V. Tiunov, design engineer of 2nd category, IPPM RAS; This email address is being protected from spambots. You need JavaScript enabled to view it.
D. A. Zheleznikov, researcher, IPPM RAS; This email address is being protected from spambots. You need JavaScript enabled to view it.

A method of logical architecturally-oriented resynthesis at the stage of technological mapping is proposed. The method is intended for digital circuits design flow for field programmable gate arrays (FPGAs). The aim of the work is to develop methods for digital circuit logical resynthesis with an emphasis on area optimization as well as integration of these methods into existing digital circuits design flows for FPGAs. FPGA architecture where programmable logic cell contains a block with programmable lookup table and a trigger connected to it is considered. The proposed logical resynthesis method for the cell in question allows to reduce the area occupied by the designed circuit of the FPGA. The method is implemented as a software module (the algorithm of which is described in the text) and tested on a set of test circuits ISCAS'89. The obtained
results indicate a significant (with an average of ~ 20 %, and up to ~ 38 %) reduction of the resulting occupied area. The method is integrated into existing domestic digital circuit design flows for FPGAs.

Key words: technology mapping; logic synthesis; design flow; Field Programmable Gate Array (FPGA); Computer Aided Design (CAD).

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