UDC 621.382
CALCULATION OF DELAY AND VOLTAGE DROP IN DIGITAL LSI INTERCONNECTIONS USING COMPACT ELECTRO-THERMAL SPICE-MODEL
K. O. Petrosyants, PhD (technical sciences), professor, MIEM HSE; This email address is being protected from spambots. You need JavaScript enabled to view it.
E. I. Batarueva, post-graduate student of the Department of electronics engineering, MIEM HSE; This email address is being protected from spambots. You need JavaScript enabled to view it.
N. I. Ryabov, PhD (technical sciences), associate professor, MIEM HSE; This email address is being protected from spambots. You need JavaScript enabled to view it.
Irregular heating of the interconnection lines leads to the distortion of transmitted signals and to the increase of time delay in particular. The aim of the work is to develop the program for calculating the interconnection model parameters (resistances and capacitances) depending on the temperature at the points along interconnection lines. To achieve this goal the following objective is set: development of program tools for delay modeling in LSI interconnections with account for thermal effects. Authors use the interconnection model in the form of distributed RC-circuit, parameters of which depend on the chip surface temperature distribution. The chip surface temperature is calculated by program tool «Overheat-MC», developed by the authors. Interconnection model parameters – resistances and capacitances of RC circuit sections, are calculated on the basis of temperature distribution along the interconnection. This approach allows to take into account the influence of chip non-uniform overheat on interconnection electrical characteristics. For the simplification of interconnection model and CPU time decrease the multi-sectional RC – model is reduced to compact Pi-shaped equivalent circuit with temperature-depended parameters. It is shown that in comparison to Pi-shaped circuit, the signal magnitude error is at most 7%, the signal phase error is 2 %. In this case, CPU time decreases on the order of 25-30 %.
Key words: LSI interconnections, reduction, electro-thermal model, signal delay in interconnections.