UDC 681.32
INVESTIGATION OF THE ASYNCRONOUS ARBITER
S. F. Tyurin, Honored Inventor of the Russian Federation, Doctor of Technical Sciences, Professor at the Department of Automation and Telemechanic Perm National Research Polytechnic University, Professor at the Department of Mathematical Support of Computer Systems Perm National Research Polytechnic University Russia; This email address is being protected from spambots. You need JavaScript enabled to view it.
Since the appearance in the 70s of the twentieth century of programmable logic – first programmable logic matrices (PLM) by Texas Instruments, and then in the 1980s – programmable logic integrated circuits – FPGAs, the attempts to use them in asynchronous circuitry are being made. However, a synchronous method for calculating logical functions is still used. Synchronization frequency is calculated for the worst case, which leads to performance decrease. In addition, timing tools occupy a large area of crystal and impair energy efficiency. The asynchronous way of processing information is devoid of these shortcomings, but it gives rise to another, more complex synthesis of asynchronous schemes. In addition, there are known difficulties using standard FPGAs, for example, in the implementation of so-called arbitrators, allowing to eliminate negative consequences of competition (races). In recent years, modified FPGAs have been proposed, which include additional elements necessary for realizing asynchronous circuits. But these elements, in turn, are also subject to the negative properties of transient processes in asynchronous circuits. The article examines a special arbiter, which is absent in synchronous FPGAs. The aim of the work is to study the features of asynchronous arbiter scheme, in which there is a nonstandard connection of inverters, the definition of transition function and the modeling of its operation as well as the development of the arbiter for radiation-hardened FPGAs.
Key words: Field-Programmable Gate Array, Arbiter, Flip-Flop.