UDC 004.27
BUILDING VARIANTS OF CONTENT ADDRESSABLE MEMORY OF KEYS FOR PARALLEL DATAFLOW COMPUTING SYSTEM «BURAN»
N. N. Levchenko, PhD (technical sciences), Head of the Department, IPPM RAS, Moscow; This email address is being protected from spambots. You need JavaScript enabled to view it.
A. S. Okunev, PhD (technical sciences), Leading Research Associate, IPPM RAS, Moscow; This email address is being protected from spambots. You need JavaScript enabled to view it.
A. V. Klimov, Senior Research Associate, IPPM RAS, Moscow; This email address is being protected from spambots. You need JavaScript enabled to view it.
D. N. Zmejev, Research Associate, IPPM RAS, Moscow; This email address is being protected from spambots. You need JavaScript enabled to view it.
The problem of preventing the overflow of content addressable memory of keys of matching processor in parallel dataflow computing system is considered. The aim of the work is the development of hardware-software methods that allow to exclude overflow of content addressable memory of keys of matching processor. The relevance of this work is the need to create a domestic high-performance computing system based on a dataflow computing model that provides high real performance on actual tasks when scaling to hundreds of thousands or more cores. In this case, nonstandard hardware solutions must be applied. The methods for preventing the overflow of content addressable memory of keys are compared. Variants of constructing content addressable memory of keys of matching processor are proposed. The results of these variants comparison are presented; advantages and disadvantages are noted. The results of modeling developed methods and variants of organizing content address able memory of keys of matching processor confirm the efficiency and correctness of the approaches proposed. As a result of the research conducted, the architecture of content addressable memory of keys of matching processor and the method that prevents its overflow are selected.
Key words: content addressable memory, matching processor, computations planning, comparison of keys.