UDC 004.021
CONFIGURATION ISSUES OF FPGA-BASED COMPUTING CLUSTERS
D. O. Shchepukhin, post-graduate student, RTU MIREA, Moscow, Russia;
orcid.org/0009-0004-9862-4053, e-mail: This email address is being protected from spambots. You need JavaScript enabled to view it.
The article considers the problem of optimally filling computing clusters of a massively parallel special ized FPGA-based accelerator in a heterogeneous system with processor cores of various types to verify the compliance of the input data stream with a set of regular expressions. The aim of the work is a mathemati cal formulation of the problem for the subsequent development of the corresponding CAD module based on it. The distribution of regular expressions across the nodes of a heterogeneous system is carried out using a specialized synthesizer, which also generates types of cores for placement in accelerator clusters. In this way, the synthesizer connects the system and RTL levels of design. Next, it all comes down to sequentially solving two subtasks using combinatorial optimization or dynamic programming methods. The solution to the problem is considered using the example of the placement of cores on the xc7a100tcsg324-1 crystal of the Artyx-7 FPGA. Assumptions are made about the need for a feedback mechanism from the topology level.
Key words: : combinatorial optimization, cluster computing, FPGA, pattern matching, programmable numerators.