UDC 004.383.3
POSSIBLE HARDWARE IMPLEMENTATION ON PROGRAMMABLE LOGIC INTEGRATED CIRCUITS OF NODES IN RECONFIGURABLE COMPUTER SYSTEM
A. I. Martyshkin, Ph.D. (Tech.), Associate Professor, Head of Programming Department, PSTU, Penza, Russia;
orcid.org/0000-0002-3358-4394, e-mail: This email address is being protected from spambots. You need JavaScript enabled to view it.
This paper is devoted to an experimental study of a reconfigurable field-programmable gate array based computing system. The main aim of the study is to conduct experiments on the control of reconfigurable nodes of this computing system. The paper describes a reconfigurable computing system based on four reconfigura-ble processors implemented on field-programmable gate array. To solve the problems associated with loss of performance in software implementation of task scheduling function, its hardware implementation is pro-posed. This improves performance and reliability of operating system, as the responsibility for software func-tions is removed from processor nodes. The paper also considers modeling of control nodes, including task manager of a reconfigurable computing system, taking into account modern element base. In order to verify the efficiency of the algorithm and the analysis of time diagrams an experiment was carried out on a proto-type of a reconfigurable computing system using digital logic analyser which provided detailed information on the signals in a system and ModelSim-Altera 10.0c simulation environment which gave accurate and reli-able results. The printed circuit board schematic developed by the author is presented to create a prototype of a reconfigurable computing system. It has been designed with modern requirements in mind, ensuring stable and efficient operation of the system. Thus, the experiment and the presented circuit board scheme allowed to get accurate results of the analysis of time diagrams of reconfigurable computer system, as well as to create a prototype which meets current requirements and has high stability and efficiency. According to experimental results, it was concluded that the proposed algorithm works as a task manager. In the final part of the article main conclusions and recommendations for further development of this scientific direction are presented
Key words: : hardware implementation, speed, task manager, operating system, performance, reconfigurable computing system, synchronisation, FPGA.