UDC 004.31
DESIGN OF PIPELINE COMPUTING DEVICES CONSIDERING TOPOLOGICAL REPRESENTATION
I. E. Tarasov, Dr. in technical sciences, Head of the Laboratory, RTU MIREA, Moscow, Russia;
orcid.org/0000-0001-6456-4794, e-mail: This email address is being protected from spambots. You need JavaScript enabled to view it.
D. V. Lulyava, junior researcher, RTU MIREA, Moscow, Russia;
orcid.org/0009-0009-9623-7777, e-mail: This email address is being protected from spambots. You need JavaScript enabled to view it.
N. A. Duksin, engineer, RTU MIREA, Moscow, Russia;
orcid.org/0009-0009-0014-7065, e-mail: This email address is being protected from spambots. You need JavaScript enabled to view it.
The problem of designing a pipeline computer to operate as part of a digital computing system is considered. The aim is to study the influence of pipeline computer architecture on the characteristics of its topological representation in order to optimize a computer according to selected optimality criteria. When designing high-performance computing systems, an important stage is the architectural design and decomposition of the system. In this case, the choice of operations for hardware acceleration depends on the characteristics of the accelerator obtained on existing hardware platform. Design at various levels: system, circuit and topological allows, on the one hand, to abstract from implementation details and increase development productivity, but on the other hand, the transition to implementation details clarifies the final characteristics of the designed accelerator for a computing system and can significantly worsen them relative to preliminary expectations. The article discusses a subclass of pipeline computing accelerators and the dependence of their size characteristics, signal propagation delay and power consumption on control system architecture. The possibility of partial compensation for the shortcomings of architectures that have simple topological implementation has been identified, at the expense of nodes that ensure pipeline integration into computing system. The authors propose to use optimization in discrete parameter space, for which a parameterized pipeline description is used.
Key words: : computing system, pipeline, architecture, FPGA, VLSI, register transfer level.