UDC 004.27
DESIGN OF PROGRAMMABLE LOGIC COMPUTING CLUSTERS
N. A. Duksin, post-graduate student, Lecturer, Computer science department, RTU MIREA, Moscow, Russia; orcid.org/0009-0009-0014-7065, e-mail: This email address is being protected from spambots. You need JavaScript enabled to view it.
The problem of designing a computing system for massively parallel data processing is considered. The aim of the work is to form the architecture of a computing system based on cluster partitioning using pro grammable numerators. This approach makes it possible to optimize data processing process, ensuring the balance between performance and flexibility of a system. In particular, the use of field programmable gate array (FPGAs) makes it possible to implement adaptive computing resources that can be reconfigured for specific data processing tasks. The problem is considered in the context of continuous flow of input data, which requires the development of effective mechanisms for distributing computing resources and control ling data flow. An approach to the organization of cluster structure of a computing device is described, in cluding methods for dynamically distributing tasks between computing cluster nodes, as well as load balanc ing algorithms, special attention is paid to the tasks of control core of designed system. Additionally, the possibility of using a partial reconfiguration approach to increase the flexibility of using the final system is explored. As a practical implementation of the proposed approach, system layout based on programmable logic integrated circuits is described.
Key words: : massively parallel computing systems, cluster computers, FPGA, RTL, pattern matching, partial reconfiguration, programmable computer unit.